DevJobs

Physical Design Power Optimization Engineer

Overview
Skills
  • Physical design EDA tools
  • Cadence
  • Physical design flows
  • Physical verification
  • PNR
  • STA
  • Synopsys
NVIDIA is looking for best-in-class Physical Design Power Engineer to join our outstanding Networking Silicon Power engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput, lowest latency and best Power! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.

What You Will Be Doing

  • Power Optimization of Physical design, of blocks/top-level/fc under challenging constraints.
  • Optimization involves all aspects of physical design chip development (RTL2GDS) - synthesis, power and clock distribution, place and route, timing closure, power and noise fixes.

What We Need To See

  • B.SC./ M.SC. or equivalent experience in Electrical Engineering/Computer Engineering.
  • 0-2 years of experience in physical design and/or BE power optimization aspects.
  • Familiarity with physical design EDA tools (such as Synopsys, Cadence, etc.).
  • Knowledge in physical design flows and methodologies (PNR, STA, physical verification) is an advantage.
  • FE design experience is an advantage.
  • Excellent problem-solving, partnership, and interpersonal skills.

NVIDIA has some of the most forward-thinking people in the world working for us. Are you a creative and autonomous engineer who loves a challenge? Are you ready to become the engineer you always wanted to be? Come and be part of the best physical design team in the industry!

JR1999236

Nvidia